英文字典中文字典


英文字典中文字典51ZiDian.com



中文字典辞典   英文字典 a   b   c   d   e   f   g   h   i   j   k   l   m   n   o   p   q   r   s   t   u   v   w   x   y   z       







请输入英文单字,中文词皆可:

goldsmith    音标拼音: [g'oldsm,ɪθ]
n. 金工,金首饰商

金工,金首饰商

goldsmith
n 1: an artisan who makes jewelry and other objects out of gold
[synonym: {goldsmith}, {goldworker}, {gold-worker}]
2: Irish writer of novels and poetry and plays and essays
(1728-1774) [synonym: {Goldsmith}, {Oliver Goldsmith}]

Goldsmith \Gold"smith`\, n. [AS. goldsmi?. See {Gold}., and
{Smith}.]
1. An artisan who manufactures vessels and ornaments, etc.,
of gold.
[1913 Webster]

2. A banker. [Obs.]
[1913 Webster]

Note: The goldsmiths of London formerly received money on
deposit because they were prepared to keep it safely.
[1913 Webster]

{Goldsmith beetle} (Zool.), a large, bright yellow, American
beetle ({Cotalpa lanigera}), of the family
{Scarab[ae]id[ae]}
[1913 Webster]

Goldsmith
(Neh. 3:8,32; Isa. 40:19; 41:7; 46:6). The word so rendered
means properly a founder or finer.


请选择你想看的字典辞典:
单词字典翻译
Goldsmith查看 Goldsmith 在百度字典中的解释百度英翻中〔查看〕
Goldsmith查看 Goldsmith 在Google字典中的解释Google英翻中〔查看〕
Goldsmith查看 Goldsmith 在Yahoo字典中的解释Yahoo英翻中〔查看〕





安装中文字典英文字典查询工具!


中文字典英文字典工具:
选择颜色:
输入中英文单字

































































英文字典中文字典相关资料:


  • EAGLE - Two label on one wire? | Forum for Electronics
    EAGLE - Two labels on one wire? Hi, Is it possible to make two or more diffrent labels for the same wire? I want to make schematic for decoupling microcontroller supply pins like this: When i'm putting VDD symbol, all labels are changed to VDD: Or how to make similar schematic for this
  • [VHDL] Read Stimuli file in VHDL | Forum for Electronics
    vhdl read Hello again, I have been looking throuhg Ashenden's Deisgner Guide to VHDL for file reading in VHDL I thought it is the best way to drive test becnh signals: have a stimuli file read in the test bench entity and give values to the different needed signals at every clock event My
  • need help to simulate the MOS varactor in Cadence
    varactor cadence AC simulation with Parametric Analysis Connect VDC=Vcontrol with AC magnitude 1mV (or 1V - it is a matter of cinvenience only) to varactor Then set AC analysis in interested frequency range Select parametric analysis with Vcontrol as sweeping variable Then use calculator
  • PMOS Turn on problem - Forum for Electronics
    I am trying to use a PMOS as a high side switch The source voltage is ~14V I am trying to create a load switch control circuit using an NMOS and resistor so that a small driver can be used for the NMOS to pull the gate of the high side PMOS to ground, turing on the PMOS when necessary I am
  • refelction coefficient calculation - Forum for Electronics
    Hello, I am looking at the following calculation for the reflection coefficient of a transmission line using the formula ((ZL - ZO) (ZL +ZO) I can understand it all apart from the last part (0 355e^j) Can someone please tell me how that figure was gained from (-0 354 + 0 030j) (216 + j15 -
  • LFSR reverse function - Forum for Electronics
    is it possible to get the reverse sequence generated by a LFSR? I need a pseudo random sequence, and the same sequence in reverse order I read that the output stream of a LFSR can be reversed by mirroring the taps This did not work, however : - - - Updated - - - It's not possible
  • Bluetoth component for delphi 7 - Forum for Electronics
    delphi bluetooth torry can someone help me to give me a link about bluetooth component for delphi 7? thanx
  • [SOLVED] cells with number of pins gt; 6 - Forum for Electronics
    get_flat_cells [get_objects_by_location -within [get_attribute [get_placement_blockages pb_0] bbox]] The above command is used to get cells from particular location How to get only the cells whose number of pins are greater than 6 -- Pruthvi
  • Doubly terminated ladder - Forum for Electronics
    HI Can any one tell me why doubly terminated LC ladder filter are used What will happen without using input resistance and output load resistance? as shown in figure attached
  • Downloading problem in ACTEL FPGA - Forum for Electronics
    Hi, I am seeing a peculiar problem, when I dumping the code into ACTEL FPGA Some times the code is not working properly But when I recompile and dump into FPGA without any modifications in code, it may work Why this problem occurs? If occurs what measures we have to take into account My





中文字典-英文字典  2005-2009